There are memory subsystems that enable parity error checking at the memory devices. For signals sent by the memory controller over the signal lines to the memory devices, the memory devices can check for parity error and trigger an error if the parity check fails. The memory controller is a single sender, and the memory devices are many receivers for the same signal. The receivers are placed sequentially on the signal line, which means that each of the memory devices receives the signals from the memory controller at a different point in time. Additionally, the memory devices share a signal line for an error alert signal. Thus, when the memory devices trigger an error there is a slightly different timing from the memory devices to the memory controller. In traditional systems, the memory devices trigger an error alert signal as soon as they detect the error, and route a signal back to the memory controller along the error alert line. Seeing that symbol corruption can occur at any point along the signal line from the controller to the last memory device, there is no way of knowing when an alert signal could reach the memory controller.
In traditional systems where the memory controllers keeps a history of commands for purposes of error recovery, the depth of the history needed to be deep enough to cover the worst-case error alert signal. The worst-case signal timing assumed the last memory device to receive the command/address signal would send an alert, which would then be routed all the way back to the memory controller.
When the speed of the processor is slow relative to the speed of signal transmission, the difference in timing has little effect on the system. However, as systems speed up, the worst-case scenario could be dozens of pipeline stages (instructions) of execution occurring while the memory controller waits for an error alert. The memory controller would need to save a history to match the number of pipeline stages to be able to perform error recovery. If the error signal from the memory devices does not reach the controller before data associated with a command arrives at the memory controller, the memory controller could latch in the wrong data. The timing of current systems is very marginal, which makes the error alert and recovery mechanisms suspect, and requires a lot of resources to perform error recovery.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.